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Job Descrption

Requirements
• At least 8 years of experience in hardware verification languages (SystemVerilog, SystemC),
• Bachelor/Master in Electrical/Computer Engineering/Engineering Science,
• Experience with UVM and coverage driven constrained random verification,
• Experience with Low power verification techniques,
• Excellent programming skills. C/C++ as well as scripting languages (Perl, tcl),
• Deep interest in computer architecture

What the job involves
• Tenstorrent is looking for an experienced Digital DV Engineer to join our team,
• At Tenstorrent you will have the chance to accelerate your career by working on challenging engineering problems with a dedicated team,
• We are looking for a DV Engineer to develop verification methodology for our products,
• Verification of Tenstorrent's digital IP and SOC logic, using advanced verification methodologies - UVM, FPGA prototyping, emulation,
• Creation of test plans,
• Writing testbenches, checkers and tests, models, assertions and... irritators,
• Creating functional coverage points,
• Reviewing verification results and metrics and, driving the verification convergence towards tape-out,
• Performance and power verification and validation of Tenstorrent's IP and SOC

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